In an integrated circuit, a clock signal having a different phase shift with the system clock signal is sometimes required for a specific function. For instance, in one method of capturing a data signal, a clock signal 90 degrees out of phase with the system clock is needed. This clock signal is normally referred to as a quadrature clock signal.
Conventionally, the quadrature clock signal can be generated by a phase splitter using analog or digital delay locked loop (DLL). A traditional phase splitter using digital DLL has four delay segments connected in series. Each of the delay segments has a plurality of delay stages to provide a quarter of clock cycle delay to an input or system clock signal. Together, the four delay lines generate four output clock signals having 90, 180, 270 and 360 degrees out of phase with the system clock signal.
Since the traditional phase splitter using digital DLL has four delay lines connected in series, each time the DLL performs a signal synchronization to generate the output clock signals, four delay stages are used, one from each delay segment. Each delay stage includes two delay gates to avoid logic inversion. Thus, the delay resolution of the traditional digital phase splitter is equal to eight delay gates. This resolution may not provide a satisfactory level of accuracy for some devices, especially for high speed devices such as new generations of memory devices.
There is a need for improving the delay resolution of digital phase splitters for producing multiple clock signals.